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FPGA-based audio codec chip interface design

Print View , by: iSee ,Total views: 22 ,Word Count: 1419 ,Date: Sat, 27 Jun 2009 Time: 11:21 AM

1 Overview

WM873l is a powerful 24-bit low-power stereo audio codec chip, which drives high-performance headphones, low-power design, controlled sampling frequency, the filter may choose to make WM8731 chips widely used in portable MP3, CD, PDA occasions. Diagram of its structure as shown in Figure 1.

FPGA-based audio codec chip <a href=interface design" />

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WM8731 includes two line inputs and microphone input and a way to adjust the volume can be carried out; built-chip ADC (analog-to-digital converter) and a choice of high-pass digital filter; the use of high-quality over-sampling rate of the structure of the DAC (digital-analog converter browser); line output and headphone output; built-in crystal oscillator, as well as configurable digital audio interface and an optional 2 or 3-wire control interface, such as microprocessors. Through the control interface controller (Control Interface) configuration of the WM8731, and then through the digital audio interface (Digtal Audio Interface) audio signals to read and write data. In this paper, the design of a FPGA-based drive module to the control interface and the WM8731 digital audio interface is converted to a common bus interface controller, so that the controller can read and write registers as an external control on the use of WM8731 chip.

2 WM8731 chip interface timing to introduce

2.1 Control Interface Timing

The WM8731 control interface has four pins, namely: MODE (the control line interface options), CSB (chip select or address select line), SDIN (data input lines) and SCLK (clock input line). It has 2 lines and 3-wire mode. 2 lines for the MPU interface, 3-wire interface is SPI compatible. Control interface of the configuration options by setting the MODE pin can be a state of completion. Select MODE to 0 for 2-wire mode, 1 for 3-wire mode. In this paper, a 2-wire control mode for the WM8731. Its timing diagram shown in Figure 2.

FPGA-based audio codec chip interface design

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2.2 Digital Audio Interface Timing

The WM8731 digital audio interface has five pins, namely: BCLK (bit clock digital audio), DACDAT (DAC digital audio data input), DACIRC (DAC sampling left / right-channel signal), ADC-DAT (ADC digital audio signal output), ADCLRC (ADC sampling left / right-channel signal).

Digital audio interface can work in the main model and from the mode. Address register for the first 0,000,111 of the 6 data set master / slave mode: "1"-based model, "0" for the slave mode. ADCDAT, / DACDAI and ADCLRC / DACLRC with the digital clock synchronization BCIK in each BCLK falling edge of a transmission. BCLK and ADCLRC / DACLRC in the main mode for the output signal from the mode for the input signal. DAC-DAT is always the input signal, ADCDAT always output signal.

Four kinds of digital output audio data to support the model: right-justified, left-justified, I2S and dsp mode. Register through the different configuration, you can set the data transmission format. Register configuration values are as follows:

0000111 Address Register 1 ~ 0 setting audio format: "11" for the DSF 'format, "10" for the I2S format, "01" for left-justified format, "00''format for the right alignment.

3 ~ 2 set word length: "11" at 32, "10" to 24 "01" to 20 "00''for 16-bit.

The four audio formats are high (MSB) first, 16 to 32. However, the data do not support 32-bit right-justified mode.

In this paper, the main mode of the left-justified data format, left-justified data format transfer in Figure 3: left-justified format, MSB in the first rising edge of BCLK effective, followed by a transmission ADCLRC or DACLRC.

FPGA-based audio codec chip interface design

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3 WM8731 chip FPGA-driven design

3.1 drive the overall design program

In this paper, the design of the drive when using the block diagram shown in Figure 4. Dual-port RAM and the drive connected to the controller with the data bus and address bus, the controller can provide a small number of control lines can be completed on the audio codec chip wM8731 control and data exchange functionality.

FPGA-based audio codec chip interface design

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Drive the internal structure of block diagram shown in Figure 5. Drive control provides the interface between the controller (includes data bus signals, address bus signals and control signals), conversion at the same time have a control unit and digital audio interface unit of the control signal; internal cache control register of words and the state of the word; control characters into the control unit is responsible for a string line sent to the WM8731, the signal transmission at the same time-tested; data WM8731 audio interface unit complete with an external dual-port RAM and the string conversion, the realization of digital audio signals to send and receive functions.

FPGA-based audio codec chip interface design

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Flooding FPGA-based audio codec chip interface design

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Table l control status register corresponding to the definition of the word

FPGA-based audio codec chip interface design

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3.2.2 Control unit conversion

When the START position control'1 'when the control word register in the serial data sent to the WM8731, when the transmission error, it will be state of the ACK register location 1. As shown in Figure 6.

FPGA-based audio codec chip interface design

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3.2.3 Digital Audio Interface Unit

When read into the digital audio flag C1 is'1 ', to receive from the WM873l chip and digital audio data into an external dual-port RAM, when the output digital audio data for the C2 flag'1' when the dual-port RAM of the audio data sent to wM8731. Shown in figure 7.

FPGA-based audio codec chip interface design

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3.3 system Simulation

Controller is given below the drive control module to write the word on the WM8731 timing simulation shown in Figure 8. Figure in the definition of the pin as shown in table 2.

FPGA-based audio codec chip interface design

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FPGA-based audio codec chip interface design

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4 Conclusion

The use of FPGA for WM8731 audio codec chip to interface circuit design, the realization of the control interface and digital audio interface of the centralized control, simplifying the WM8731 audio codec chip the use of steps with good scalability, the use of simple and convenient, easy to upgrade, etc. advantages to other chip interface design has some reference value.


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